Presently the most widely used integrated circuit is the dynamic random access memory (DRAM) and the most common form of memory cell that is assembled in large arrays to form a DRAM comprises a switch, generally a metal-oxide silicon field effect transistor (MOSFET), in series with a capacitor. Binary digits to be stored are written into and read out of the capacitor under control of the switch. A common form of such capacitor comprises a vertical trench in the silicon chip that houses the device, the trench being filled with doped polysilicon, and the fill being isolated from the rest of the chip by a dielectric layer, typically of a silicon oxynitride. A low resistance conductive connection of doped polysilicon, generally called a strap, is provided in the chip between the doped polysilicon fill that serves as the storage node and the one of the two current terminals in the bulk silicon of the MOSFET that shares a storage node, typically described as the source of the MOSFET. It is to be noted that the source and drain of a MOSFET of a memory cell of the type described herein reverse during write-in and read-out operations. In addition, a shallow isolation trench, typically of silicon oxide, isolates from one another individual cells of the array that form the DRAM.
The usual process for forming such a DRAM results in a strap that is buried below the original surface of the chip and so is of reduced effectiveness. Moreover, such process typically requires three polysilicon deposition steps and a chemical mechanical polishing (CMP) with each such deposition step. Moreover, the size of the strap connection is dependent on several steps. To compensate for possible shortcomings in any of these steps, it is customary to be conservative and so the design typically calls for extra depth of the trench, which further complicates the process.